IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology

Authors:
B. W. Curran;Y. H. Chan;P. T. Wu;P. J. Camporese;G. A. Northrop;R. F. Hatch;L. B. Lacey;J. P. Eckhardt;D. T. Hui;H. H. Smith
Affiliations:
IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Server Group, Poughkeepsie, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York
Venue:
IBM Journal of Research and Development
Year:
2002

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Abstract

The IBM eServer z900 microprocessor is a seventh-generation zSeries™ (formerly S/390®) CMOS design which has achieved 1.3-GHz operation. This paper describes the 0.18-µm bulk CMOS, seven-level copper metal process and the high-frequency circuit, integration, and design methodologies developed to achieve this operation. The microprocessor was floorplanned to closely mimic the flow of the microarchitecture pipeline and reduce the communication delay overhead between units. Novel circuit techniques were used in the implementation of the arrays and cache hit detection logic to save power and reduce circuit complexity without sacrificing performance. A four-dimensional gate library and novel synthesis algorithms were developed to yield synthesized control implementations with the performance characteristics of a fully custom circuit design.