Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Quantifying Design Quality Through Design Experiments
IEEE Design & Test
microSPARCTM: A Case Study of Scan-Based Debug
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Neighbor selection for variance reduction in I_DDQ and other parametric data
Proceedings of the IEEE International Test Conference 2001
Optimal production test times through adaptive test programming
Proceedings of the IEEE International Test Conference 2001
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
Proceedings of the IEEE International Test Conference 2001
Silicon debug of a co-processor array for video applications
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Delta Iddq for Testing Reliability
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Logic Mapping on a Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Effective Diagnosis Method to Support Yield Improvement
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Screening MinVDD Outliers Using Feed-Forward Voltage Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
System performance management for the S/390 parallel enterprise server G5
IBM Journal of Research and Development
IBM S/390 parallel enterprise server G5 fault tolerance: a historical perspective
IBM Journal of Research and Development
RAS strategy for IBM S/390 G5 and G6
IBM Journal of Research and Development
RAS design for the IBM eServer z900
IBM Journal of Research and Development
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
IBM Journal of Research and Development
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Evolving fault tolerant digital circuitry: comparing population-based and correlation-based methods
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
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Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing before the ICs are shipped to the customer. In this paper, we show that techniques and tools used in the testing field can also be (re-)used to create value to (1) designers, (2) manufacturers, and (3) customers alike. First, we show how the test infrastructure can be used to detect, diagnose, and correct design errors in prototype silicon. Secondly, we discuss how test results are used to improve the manufacturing process and hence production yield. Finally, we present test technologies that enable systems of high reliability for safety-critical applications.