Neighbor selection for variance reduction in I_DDQ and other parametric data

Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort

IEEE Design & Test

Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs

IEEE Design & Test

Nanometer Design: What are the Requirements for Manufacturing Test?

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Built-in Current Sensor for "I{DDQ} Testing of Deep Submicron Digital CMOS ICs

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

IDDX-based test methods: A survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)

IDDQ data analysis using neighbor current ratios

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip

Creating Value Through Test

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

IC Outlier Identification Using Multiple Test Metrics

IEEE Design & Test

DFM Metrics for Standard Cells

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

A new delay test based on delay defect detection within slack intervals (DDSI)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Quality improvement and cost reduction using statistical outlier methods

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design

Adaptive reduction of the frequency search space for multi-vdd digital circuits

Proceedings of the Conference on Design, Automation and Test in Europe