Neighbor selection for variance reduction in I_DDQ and other parametric data
Proceedings of the IEEE International Test Conference 2001
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Delta Iddq for Testing Reliability
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Screening MinVDD Outliers Using Feed-Forward Voltage Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
On test conditions for the detection of open defects
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functional constraints vs. test compression in scan-based delay testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
Scan Test Response Compaction Combined with Diagnosis Capabilities
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
Editor's note: Structured delay tests have been around for years, but how effectively do they identify defective silicon, even at reduced frequency? How much overkill is associated with their use? The authors present data from industrial circuits aimed at these and other aspects of speed testing.驴Ken Butler, Texas Instruments