High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Autonomic Microprocessor Execution via Self-Repairing Arrays
IEEE Transactions on Dependable and Secure Computing
Improving Transition Delay Test Using a Hybrid Method
IEEE Design & Test
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Test generation in the presence of timing exceptions and constraints
Proceedings of the 44th annual Design Automation Conference
Scan Test Response Compaction Combined with Diagnosis Capabilities
Journal of Electronic Testing: Theory and Applications
Optimal margin computation for at-speed test
Proceedings of the conference on Design, automation and test in Europe
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Optimal test margin computation for at-speed structural test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel faster-than-at-speed transition-delay test method considering IR-drop effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Improved launch for higher TDF coverage with fewer test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Choose-your-own-adventure routing: Lightweight load-time defect avoidance
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Journal of Electronic Testing: Theory and Applications
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The semiconductor industry as a whole is growing increasingly concerned about the possible presence of delay-inducing defects. There exist structured test generation and application techniques which can detect them, but there are many practical issues associated with their use. These problems are particularly acute when using low cost test equipment. In this paper, we describe an overall approach for implementing scan-based delay testing with emphasis on low-cost test.