Controllability of Static CMOS Circuits for Timing Characterization

Authors:
Ramyanshu Datta;Ravi Gupta;Antony Sebastine;Jacob A. Abraham;Manuel D'Abreu
Affiliations:
The University of Texas at Austin, Austin, USA;Freescale Semiconductors, Austin, USA;ARM Corporation, Austin, USA;The University of Texas at Austin, Austin, USA;SanDisk Corporation, Milpitas, USA
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2008

Citing 16
Cited 0

Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Noise in deep submicron digital design

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A method of delay fault test generation

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering

IEEE Design & Test
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Delay Testing with Clock Control: An Alternative to Enhanced Scan

Proceedings of the IEEE International Test Conference
Skewed-Load Transition Test: Part 2, Coverage

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability

DAC '77 Proceedings of the 14th Design Automation Conference
Applying two-pattern tests using scan-mapping

VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges

ITC '02 Proceedings of the 2002 IEEE International Test Conference
The Test and Debug Features of the AMD-K7TM Microprocessor

ITC '99 Proceedings of the 1999 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing

IEEE Design & Test
Robust System Design with Built-In Soft-Error Resilience

Computer
At-Speed Transition Fault Testing With Low Speed Scan Enable

VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
An Experimental Delay Test Generator for LSI Logic

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.