Clock grouping: a low cost DFT methodology for delay testing
DAC '94 Proceedings of the 31st annual Design Automation Conference
Quality considerations in delay fault testing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Path delay ATPG for standard scan design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Delay Test Generation: A Hardware Perspective
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Generator choices for delay test
ATS '95 Proceedings of the 4th Asian Test Symposium
Effects of Multi-cycle Sensitization on Delay Tests
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Too Much Delay Fault Coverage Is a Bad Thing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Detection of multiple transitions in delay fault test of SPARC64 microprocessor
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
DFT timing design methodology for at-speed BIST
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
STEAC: a platform for automatic SOC test integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of delay test quality and its application to test generation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Conflict driven scan chain configuration for high transition fault coverage and low test power
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Improved launch for higher TDF coverage with fewer test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flip-flop selection for partial enhanced scan to reduce transition test data volume
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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