High Noon on the Electronic Frontier: Conceptual Issues in Cyberspace
High Noon on the Electronic Frontier: Conceptual Issues in Cyberspace
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Design and Test of an Integrated Cryptochip
IEEE Design & Test
Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Tamper Resistance Mechanisms for Secure, Embedded Systems
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks
IEEE Transactions on Dependable and Secure Computing
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Secure scan: a design-for-test architecture for crypto chips
Proceedings of the 42nd annual Design Automation Conference
Test Control for Secure Scan Designs
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Securing Scan Design Using Lock and Key Technique
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Tamper resistance: a cautionary note
WOEC'96 Proceedings of the 2nd conference on Proceedings of the Second USENIX Workshop on Electronic Commerce - Volume 2
On the importance of checking cryptographic protocols for faults
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 46th Annual Design Automation Conference
Secure and testable scan design using extended de Bruijn graphs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Secure scan design using shift register equivalents against differential behavior attack
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection
Journal of Electronic Testing: Theory and Applications
STEP: a unified design methodology for secure test and IP core protection
Proceedings of the great lakes symposium on VLSI
Nanoscale technologies: prospect or hazard to dependable and secure computing?
LADC'07 Proceedings of the Third Latin-American conference on Dependable Computing
PUF-based secure test wrapper design for cryptographic SoC testing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be used as a means to breach chip security. In this paper, we propose a technique, called Lock & Key, to neutralize the potential for scan-based side-channel attacks. It is very difficult to implement an all inclusive security strategy, but by knowing the attacker, a suitable strategy can be devised. The Lock & Key technique provides a flexible security strategy to modern designs without significant changes to scan test practices. Using this technique, the scan chains are divided into smaller subchains. With the inclusion of a test security controller, access to subchains are randomized when being accessed by an unauthorized user. Random access reduces repeatability and predictability making reverse engineering more difficult. Without proper authorization, an attacker would need to unveil several layers of security before gaining proper access to the scan chain in order to exploit it. The proposed Lock & Key technique is design independent while maintaining a relatively low area overhead.