Logic testing and design for testability
Logic testing and design for testability
Design and Test of an Integrated Cryptochip
IEEE Design & Test
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Easily Testable Sequential Machines with Extra Inputs
IEEE Transactions on Computers
Securing Scan Control in Crypto Chips
Journal of Electronic Testing: Theory and Applications
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
Partial Scan Approach for Secret Information Protection
ETS '09 Proceedings of the 2009 European Test Symposium
SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Secure and testable scan design using extended de Bruijn graphs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Secure Scan: A Design-for-Test Architecture for Crypto Chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Secured Flipped Scan-Chain Model for Crypto-Architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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There is a need for an efficient design-for-testability to satisfy both testability and security of digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR equivalents). However, SR equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based side-channel attack called differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those extended scan circuits, we introduce differential-behavior equivalent relation, and clarify the number of SR-equivalent extended scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.