Secure scan: a design-for-test architecture for crypto chips
Proceedings of the 42nd annual Design Automation Conference
Securing Scan Control in Crypto Chips
Journal of Electronic Testing: Theory and Applications
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
A Secure Test Technique for Pipelined Advanced Encryption Standard
IEICE - Transactions on Information and Systems
Secure and testable scan design using extended de Bruijn graphs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Scan-based attacks on linear feedback shift register based stream ciphers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Secure scan design using shift register equivalents against differential behavior attack
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection
Journal of Electronic Testing: Theory and Applications
STEP: a unified design methodology for secure test and IP core protection
Proceedings of the great lakes symposium on VLSI
A new scan attack on RSA in presence of industrial countermeasures
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
PUF-based secure test wrapper design for cryptographic SoC testing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed.