The Honeynet Project: Trapping the Hackers
IEEE Security and Privacy
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
EPIC: ending piracy of integrated circuits
Proceedings of the conference on Design, automation and test in Europe
SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the importance of checking cryptographic protocols for faults
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
Secure and testable scan design using extended de Bruijn graphs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SSTKR: Secure and Testable Scan Design through Test Key Randomization
ATS '11 Proceedings of the 2011 Asian Test Symposium
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Secured Flipped Scan-Chain Model for Crypto-Architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Intellectual property (IP) core based embedded systems design is a pervasive practice in the semiconductor industry due to shorter time-to-market and tougher cost competitions. Protecting the design information in these IP cores and securing test from various attacks are two emerging challenges in today's embedded systems design. Recently reported techniques address these challenges considering secure test and IP core protection separately. However, for ensuring high security during IP core functionality and also during test, joint consideration of secure test and IP core protection is much needed. In this paper, we propose a novel and unified design methodology, called STEP (Secure TEst and IP core Protection), which addresses the joint objective of secure test and IP core protection. The aim of STEP design methodology is to achieve high security at low system cost using the same key integrated hardware during test and IP core functionality. We evaluate the effectiveness of STEP design methodology considering advanced encryption standard (AES) system as a case study. We show that proposed design methodology benefits from high security and test accuracy, requiring up to 9% higher area and 20% power overheads.