Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Non-reversible VHDL source-source encryption
EURO-DAC '94 Proceedings of the conference on European design automation
Wavelets and subband coding
Watermarking techniques for intellectual property protection
DAC '98 Proceedings of the 35th annual Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Generalized Feedback Shift Register Pseudorandom Number Algorithm
Journal of the ACM (JACM)
Digital watermarking
Modern VLSI Design
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
Journal of VLSI Signal Processing Systems
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies
Journal of VLSI Signal Processing Systems
Zero overhead watermarking technique for FPGA designs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Behavioral synthesis techniques for intellectual property protection
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)
Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)
Watermarking techniques for electronic circuit design
IWDW'02 Proceedings of the 1st international conference on Digital watermarking
Soft IP protection: watermarking HDL codes
IH'04 Proceedings of the 6th international conference on Information Hiding
Digital watermarking for copyright protection: a. communications perspective
IEEE Communications Magazine
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fingerprinting techniques for field-programmable gate array intellectual property protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective iterative techniques for fingerprinting design IP
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Protecting Combinational Logic Synthesis Solutions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware protection and authentication through netlist level obfuscation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IPR protection in IC's using watermarks
Proceedings of the First International Conference on Intelligent Interactive Technologies and Multimedia
SoC: a real platform for IP reuse, IP infringement, and IP protection
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
STEP: a unified design methodology for secure test and IP core protection
Proceedings of the great lakes symposium on VLSI
Secure public verification of IP marks in FPGA design through a zero-knowledge protocol
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RFID based access control protection scheme for SRAM FPGA IP cores
Microprocessors & Microsystems
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In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also indudes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.