Watermarking techniques for intellectual property protection
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Digital watermarking
CAD-based security, cryptography, and digital rights management
Proceedings of the 44th annual Design Automation Conference
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Remote activation of ICs for piracy prevention and digital right management
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
EPIC: ending piracy of integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Security against hardware Trojan through a novel application of design obfuscation
Proceedings of the 2009 International Conference on Computer-Aided Design
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated circuits metering for piracy protection and digital rights management: an overview
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
An efficient locking and unlocking method of sequential systems
Proceedings of the 2012 ACM Research in Applied Computation Symposium
CLIP: circuit level IC protection through direct injection of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead
Journal of Electronic Testing: Theory and Applications
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Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System-on-Chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs and to prevent revenue loss due to IP piracy. In this paper, we propose a novel design methodology for hardware IP protection and authentication using netlist level authentication. The proposed methodology can be integrated in the SoC design and manufacturing flow to provide hardware protection to the IP vendors, the chip designer, and the system designer. Simulation results on ISCAS-89 benchmark circuits show that we can achieve high levels of security through a well-formulated obfuscation scheme at less than 10% area overhead under delay constraint.