Watermarking techniques for intellectual property protection
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fundamentals of modern VLSI devices
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Robust techniques for watermarking sequential circuit designs
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CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Differential Cryptanalysis of DES-like Cryptosystems
CRYPTO '90 Proceedings of the 10th Annual International Cryptology Conference on Advances in Cryptology
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A Public-Key Watermarking Technique for IP Designs
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Remote activation of ICs for piracy prevention and digital right management
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
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Proceedings of the conference on Design, automation and test in Europe
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Hardware protection and authentication through netlist level obfuscation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
IC activation and user authentication for security-sensitive systems
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
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CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Analysis and design of active IC metering schemes
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
Secure IP-block distribution for hardware devices
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
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The disaggregation of the semiconductor design and manufacturing process has resulted in integrated circuit (IC) piracy becoming an important concern to the semiconductor industry. To address this concern, we present a method for achieving robust IC protection at the circuit level through direct injection of process variations. In the proposed approach, the circuit is enhanced by including process variation (PV) sensors and modifying the design during synthesis to inject the outputs of the PV sensors into the logic at carefully selected nodes. As a result, each fabricated IC is rendered inoperative unless a unique per-chip unlocking key is applied. After fabrication, the response of each chip to specially generated test vectors is used to construct the correct per-chip unlocking key. We propose a methodology to automatically modify circuits by identifying pairs of injection and correction points, while avoiding delay penalty and minimizing area overheads. We propose the use of a cryptographic preprocessor to separate the internal key used from the external unlocking key, further enhancing the resistance of the proposed approach against several attacks. Our methodology is scalable to the key size and requires only a small area overhead to achieve reasonable security levels (e.g., 7% for 64-bit keys in a 8 k gate design). We analyze the security of the proposed technique under several attack scenarios and believe that it offers robust protection against a wide range of attacks.