Digital watermarking
Computational Forensic Techniques for Intellectual Property Protection
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Cryptanalysis of UCLA Watermarking Schemes for Intellectual Property Protection
IH '02 Revised Papers from the 5th International Workshop on Information Hiding
Techniques for the creation of digital watermarks in sequential circuit designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis-for-testability watermarking for field authenticatioil of VLSI intellectual property
IEEE Transactions on Circuits and Systems Part I: Regular Papers
SoC: a real platform for IP reuse, IP infringement, and IP protection
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Secure public verification of IP marks in FPGA design through a zero-knowledge protocol
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CLIP: circuit level IC protection through direct injection of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Sharing IP blocks in today's competitive market poses significant high security risks. Creators and owners of IP designs want assurances that their content will not be illegally redistributed by consumers, and consumers want assurances that the content they buy is legitimate. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, we propose a new approach for watermarking IP designs based on the embedding of the ownership proof as part of the IP design's FSM. The approach utilizes coinciding as well as, un-used transitions in the state transition graph of the design. Our approach increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. We also defin evaluation criteria for our approach, and us experimental measures to prove its robustness.