Identity-based cryptosystems and signature schemes
Proceedings of CRYPTO 84 on Advances in cryptology
IBM Systems Journal
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Discrete Mathematics
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
On Synthesizing Circuits With Implicit Testability Constraints
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A new approach to scan chain reordering using physical design information
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Proceedings of the IEEE International Test Conference 2001
Synthesis-for-scan and scan chain ordering
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Asynchronous multiple scan chains
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing
ATS '04 Proceedings of the 13th Asian Test Symposium
A Public-Key Watermarking Technique for IP Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Behavioral synthesis techniques for intellectual property protection
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VLSI Design IP Protection: Solutions, New Challenges, and Opportunities
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
An efficient SoC test technique by reusing on/off-chip bus bridge
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Evolution toward reconfigurable user equipment
IEEE Communications Magazine
Test-point insertion: scan paths through functional logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for the creation of digital watermarks in sequential circuit designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Protecting Combinational Logic Synthesis Solutions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RFID based access control protection scheme for SRAM FPGA IP cores
Microprocessors & Microsystems
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Most VLSI watermarking techniques do not allow different authorships of multiple Intellectual Property (IP) cores to be detected directly in the field after the IPs have been integrated, fabricated and packaged into chip. Watermark inserted at the design-for-testability (DfT) stage makes its direct detection after chip packaging possible, but it protects only the downstream placement-and-routing design, and is vulnerable to removal attack as the test logic is independent of the functional logic. In this paper, we propose a publicly detectable watermarking scheme to bridge the gap between IP protection and IP management. The design is watermarked by means of synthesis-for-testability (SfT), where the test and functional logics of the IP are merged and synthesized together without using scannable flip-flops. Watermarked constraints are imposed on the scan chain ordering problem in the SfT process so that ownership of the embedded IP can be publicly identified by lawful IP providers, buyers and consumers by injecting a specific test vector in the field. The overhead due to the watermark insertion is minimized by a nearest neighbor search algorithm for flip-flop reordering. As the scan function is an integral part of the design in the synthesis process of the IP creation, the watermark is harder to be removed relative to other scan chain watermarking schemes whose test circuits are logically independent of the IP functionality. To deter and track IP fraudulence by the licensees, a provable mechanism is proposed to enable multiple authorships of different IP cores in a single chip to be publicly authenticated in the field. Experiments performed with ISCAS89 and LGSyn93 benchmark circuits show that the proposed watermarked designs have low design overheads, and the probabilities of coincidence and removal redluce rapidly with increased watermark and scan chain length.