Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing

Authors:
Ho Fai Ko;Nicola Nicolici
Affiliations:
McMaster University;McMaster University
Venue:
ATS '04 Proceedings of the 13th Asian Test Symposium
Year:
2004

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Abstract

This paper introduces a new method to construct functional scan chains at the register-transfer level aimed at increasing the delay fault coverage when using the skewed-load test application strategy. It is shown how by consciously creating scan paths prior to logic synthesis, both the transition delay fault coverage and circuit speed can be improved.