Intellectual property protection in the EDA industry
DAC '94 Proceedings of the 31st annual Design Automation Conference
Signature hiding techniques for FPGA intellectual property protection
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Robust FPGA intellectual property protection through multiple small watermarks
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Cryptographic rights management of FPGA intellectual property cores
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Secure Configuration of Field Programmable Gate Arrays
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Zero overhead watermarking technique for FPGA designs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
An automated, FPGA-based reconfigurable, low-power RFID tag
Microprocessors & Microsystems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Robust Intellectual Property Protection for VLSI Physical Design
ICIT '07 Proceedings of the 10th International Conference on Information Technology
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
IP protection platform based on watermarking technique
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Using the Power Side Channel of FPGAs for Communication
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Synthesis-for-testability watermarking for field authenticatioil of VLSI intellectual property
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Extracting secret keys from integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SoC: a real platform for IP reuse, IP infringement, and IP protection
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Offline hardware/software authentication for reconfigurable platforms
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Read-proof hardware from protective coatings
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
RF authenticated protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
Partial-encryption technique for intellectual property protection of FPGA-based products
IEEE Transactions on Consumer Electronics
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fingerprinting techniques for field-programmable gate array intellectual property protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publicly detectable watermarking for intellectual property authentication in VLSI design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective iterative techniques for fingerprinting design IP
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Time-constrained Watermarking Technique on FPGA
ICICEE '12 Proceedings of the 2012 International Conference on Industrial Control and Electronics Engineering
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Field-programmable gate-array (FPGA) based hardware IP cores have emerged as an integral part of modern SOC designs. IP trading plays central role in Electronic Design Automation (EDA) industry. While the potential of IP infringement is growing fast, the global awareness of IP protection remains low. In this work, we propose a Radio Frequency Identification (RFID) based protection scheme for Intellectual Property Protection (IPP) of Static Random Access Memory (SRAM) FPGA IP cores that overcome the limitations of existing IPP techniques. Here, three types of reconfigurable RFID tags is realised in order to support the incorporation of the proposed RFID based security scheme in all the reconfigurable FPGA devices of Xilinx family. Also a special tag bypass feature is employed to increase the suitability of proposed scheme as an IPP technique for reconfigurable IP cores. The proposed scheme supports safe exchange of reconfigurable FPGA IP cores between IP providers and system developers. The results derived from the testing of hardware prototype used for the evaluation of the proposed scheme are quite encouraging and shows that the proposed security feature can be incorporated into the reconfigurable IP cores of any functionality without significant performance degradation of the reconfigurable IP cores.