Zero overhead watermarking technique for FPGA designs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
RF authenticated protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
Secure public verification of IP marks in FPGA design through a zero-knowledge protocol
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RF authenticated reconfiguration-based access control protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
RFID based access control protection scheme for SRAM FPGA IP cores
Microprocessors & Microsystems
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The configuration-data sequence of a field-programmable gate array (FPGA) is an intellectual property (IP) of the original designer. This paper proposes a partial-encryption (PE) technique for IP protection of configuration-data sequences by means of increasing the reverse-engineering cost. The PE technique encrypts a few selected data of the sequence. These data are selected in a judicious way such that, when a rival competitor copies the partially encrypted sequence into a cloned product, the cloned product performs the expected task to a certain degree of correctness but not absolutely error-free. Debugging is required. It is shown that, without an initial knowledge that a reverse-engineering countermeasure is employed, the PE technique outperforms the full-encryption technique in terms of the reverse-engineering cost. This paper describes implementation details of the proposed PE technique. Issues regarding system designs that embed hidden imperfections are also discussed