Signature hiding techniques for FPGA intellectual property protection
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Robust FPGA intellectual property protection through multiple small watermarks
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Publicly detectable techniques for the protection virtual components
Proceedings of the 38th annual Design Automation Conference
Keyless Public Watermarking for Intellectual Property Authentication
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Zero overhead watermarking technique for FPGA designs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Overcoming the obstacles of zero-knowledge watermark detection
Proceedings of the 2004 workshop on Multimedia and security
A Public-Key Watermarking Technique for IP Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Zero-knowledge watermark detection resistant to ambiguity attacks
MM&Sec '06 Proceedings of the 8th workshop on Multimedia and security
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Robust Intellectual Property Protection for VLSI Physical Design
ICIT '07 Proceedings of the 10th International Conference on Information Technology
Power Signature Watermarking of IP Cores for FPGAs
Journal of Signal Processing Systems
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Verifying the authenticity of chip designs with the DesignTag system
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partial-encryption technique for intellectual property protection of FPGA-based products
IEEE Transactions on Consumer Electronics
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fingerprinting techniques for field-programmable gate array intellectual property protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In nanometer technology regime, design components mandate their reuse to meet the complex design challenges and hence comprise Intellectual Property (IP). Unauthorized reuse raises major security issues. IP mark(s) is embedded into a design for establishing the veracity of a legal IP owner/buyer. However, methods for trustworthy public verification of IP marks are not secure. For field-programmable gate-array (FPGA) designs, marks become prone to tampering, and even being overridden by an attacker's signature after public verification. In order to ensure trustworthy yet leakage-proof public verification based on the marks hidden in a FPGA design, we propose a zero-knowledge protocol Verify_ZKP. It is an interactive two-person game between the prover and the verifier. This protocol is fast, incurs no additional design overhead, and needs no centralized signature database. We establish that Verify_ZKP satisfies zero-knowledge property, and introduce statistical metrics to measure its robustness. We have simulated our protocol for IWLS'05 FPGA benchmarks. Experimental results on robustness and overhead are very encouraging.