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Hardware protection and authentication through netlist level obfuscation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Logic encryption: a fault analysis perspective
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Security analysis of integrated circuit camouflaging
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Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.