Watermarking techniques for intellectual property protection
DAC '98 Proceedings of the 35th annual Design Automation Conference
Robust IP watermarking methodologies for physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Avalanche Characteristics of Substitution-Permutation Encryption Networks
IEEE Transactions on Computers
Behavioral synthesis techniques for intellectual property protection
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
The State-of-the-Art in IC Reverse Engineering
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preventing IC Piracy Using Reconfigurable Logic Barriers
IEEE Design & Test
Ending Piracy of Integrated Circuits
Computer
The state-of-the-art in semiconductor reverse engineering
Proceedings of the 48th Design Automation Conference
Security analysis of logic obfuscation
Proceedings of the 49th Annual Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reverse engineering digital circuits using functional analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Logic encryption: a fault analysis perspective
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hardware security: threat models and metrics
Proceedings of the International Conference on Computer-Aided Design
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Camouflaging is a layout-level technique that hampers an attacker from reverse engineering by introducing, in one embodiment, dummy contacts into the layout. By using a mix of real and dummy contacts, one can camouflage a standard cell whose functionality can be one of many. If an attacker cannot resolve the functionality of a camouflaged gate, he/she will extract an incorrect netlist. In this paper, we analyze the feasibility of identifying the functionality of camouflaged gates. We also propose techniques to make the dummy contact-based IC camouflaging technique resilient to reverse engineering. Furthermore, we judiciously select gates to camouflage by using techniques which ensure that the outputs of the extracted netlist are controllably corrupted. The techniques leverage IC testing principles such as justification and sensitization. The proposed techniques are evaluated using ISCAS benchmark circuits and OpenSparc T1 microprocessor controllers.