Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An approximate timing analysis method for datapath circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
General modeling and technology-mapping technique for LUT-based FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Approximate timing analysis of combinational circuits under the XBD0 model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Reverse Engineering and Design Recovery: A Taxonomy
IEEE Software
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High-Level Test Generation Using Symbolic Scheduling
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Functional timing analysis for IP characterization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Candidate subcircuits for functional module identification in logic circuits
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Generalized symmetries in boolean functions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Low power gate-level design with mixed-Vth (MVT) techniques
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design of mixed gates for leakage reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective
Journal of Systems Architecture: the EUROMICRO Journal
The Alex language for circuit description
Programming and Computing Software
Minimizing leakage: what if every gate could have its individual threshold voltage?
AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling
Expert Systems with Applications: An International Journal
C is for circuits: capturing FPGA circuits as sequential code for portability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the conference on Design, automation and test in Europe
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Investigating data preprocessing methods for circuit complexity models
Expert Systems with Applications: An International Journal
Static Timing Model Extraction for Combinational Circuits
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Manufacturability-Aware Design of Standard Cells
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A two-step hierarchical algorithm for model-based diagnosis
AAAI'06 Proceedings of the 21st national conference on Artificial intelligence - Volume 1
Computing minimal diagnoses by greedy stochastic search
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 2
Computing observation vectors for max-fault min-cardinality diagnoses
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 2
Hierarchical diagnosis of multiple faults
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compacting test vector sets via strategic use of implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Using logic-based reduction for adversarial component recovery
Proceedings of the 2010 ACM Symposium on Applied Computing
Fault-tolerant synthesis using non-uniform redundancy
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A Java based component identification tool for measuring the strength of circuit protections
Proceedings of the Sixth Annual Workshop on Cyber Security and Information Intelligence Research
A benchmark diagnostic model generation system
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans - Special issue on model-based diagnostics
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Gate-level redundancy: a new design-for reliability paradigm for nanotechnologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximate model-based diagnosis using greedy stochastic search
Journal of Artificial Intelligence Research
A model-based active testing approach to sequential diagnosis
Journal of Artificial Intelligence Research
Approximate quantifier elimination for propositional boolean formulae
NFM'11 Proceedings of the Third international conference on NASA Formal methods
DISTROY: detecting integrated circuit Trojans with compressive measurements
HotSec'11 Proceedings of the 6th USENIX conference on Hot topics in security
Sequential diagnosis by abstraction
Journal of Artificial Intelligence Research
Optimal utilization of available reconfigurable hardware resources
Computers and Electrical Engineering
A topological-based method for allocating sensors by using CSP techniques
CAEPIA'05 Proceedings of the 11th Spanish association conference on Current Topics in Artificial Intelligence
Biologically-Inspired optimization of circuit performance and leakage: a comparative study
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Securing netlist-level FPGA design through exploiting process variation and degradation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Delay constrained register transfer level dynamic power estimation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Deterministic circuit variation for anti-tamper applications
Proceedings of the Seventh Annual Workshop on Cyber Security and Information Intelligence Research
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Scalable sampling methodology for logic simulation: reduced-ordered Monte Carlo
Proceedings of the International Conference on Computer-Aided Design
Reverse engineering digital circuits using functional analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Event pool structures for PDES on many-core Beowulf clusters
Proceedings of the 2013 ACM SIGSIM conference on Principles of advanced discrete simulation
Input vector monitoring on line concurrent BIST based on multilevel decoding logic
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Accurate and effective algorithm for estimating the reliability of digital combinational circuits
Proceedings of the 46th Annual Simulation Symposium
Security analysis of integrated circuit camouflaging
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
Machine-learning-based circuit synthesis
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
Journal of Electronic Testing: Theory and Applications
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Digital designers normally proceed from behavioral specification to logic circuit; rarely do they need to go in the reverse direction. One such situation is examined here: recovering the high-level specifications of a popular set of benchmark logic circuits. The authors present their methodology and experience in reverse engineering the ISCAS-85 circuits. They also discuss a few of the practical uses of the resulting high-level benchmarks and make them available for other researchers to use.