Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
An MTCMOS design methodology and its application to mobile computing
Proceedings of the 2003 international symposium on Low power electronics and design
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
A novel synthesis approach for active leakage power reduction using dynamic supply gating
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Temporal and spatial idleness exploitation for optimal-grained leakage control
Proceedings of the 2009 International Conference on Computer-Aided Design
Dynamic characteristics of power gating during mode transition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leveraging rule-based designs for automatic power domain partitioning
Proceedings of the International Conference on Computer-Aided Design
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Energy-efficient performance has emerged as the key design objective of high-performance logic circuits to address power-induced reliability concerns and battery life requirements in portable devices. In the sub-65nm technology regime, these problems continue to grow as leakage power becomes the predominant form of power consumption. Among numerous power reduction techniques employed at the circuit and architectural levels, supply gating has been proven to be very effective for standby power reduction. In this paper, we propose application of fine-grained supply gating to large complex circuits for active leakage and dynamic power reduction. A design methodology and associated CAD tool is developed to synthesize combinational logic using hypergraph partitioning and Shannon decomposition, which reduces both leakage and switching power by disabling unused logic dynamically in small clusters of gates. Simulation results for a set of ISCAS-85 benchmarks show that the proposed approach can achieve up to 40% saving in total power in active mode (and up to 37% saving in standby power) with negligible impact on performance and die area for a predictive 32 nm technology.