Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches

Authors:
Somnath Paul;Saibal Mukhopadhyay;Swarup Bhunia
Affiliations:
Case Western Reserve University, Cleveland, OH;Georgia Institute of Technology, Atlanta, Georgia;Case Western Reserve University, Cleveland, OH
Venue:
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Year:
2008

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Abstract

Research efforts to develop a novel memory technology that combines the desired traits of non-volatility, high endurance, high speed and low power have resulted in the emergence of Spin Torque Transfer-RAM (STTRAM) as a promising next generation universal memory. However, the prospect of developing a non-volatile FPGA framework with STTRAM exploiting its high integration density remains largely unexplored. In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework; identify the key design challenges; and propose optimization techniques at circuit, architecture and application mapping levels. Simulation results show that a STTRAM based optimized FPGA framework achieves an average improvement of 48.38% in area, 22.28% in delay and 16.1% in dynamic power for ISCAS benchmark circuits over a conventional CMOS based FPGA design.