Timed shared circuits: a power-efficient design style and synthesis tool
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Life is CMOS: why chase the life after?
Proceedings of the 39th annual Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low power synthesis of dynamic logic circuits using fine-grained clock gating
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 2006 international symposium on Low power electronics and design
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
Proceedings of the conference on Design, automation and test in Europe
Low-Power and testable circuit synthesis using Shannon decomposition
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Temporal and spatial idleness exploitation for optimal-grained leakage control
Proceedings of the 2009 International Conference on Computer-Aided Design
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An approximation algorithm for cofactoring-based synthesis
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Dynamic characteristics of power gating during mode transition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Architecture and Code Optimization (TACO)
Synthesis of P-circuits for logic restructuring
Integration, the VLSI Journal
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Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode. We present a novel low-cost design methodology with associated synthesis flow for reducing both switching and active leakage power using dynamic supply gating. A logic synthesis approach based on Shannon expansion is proposed that dynamically applies supply gating to idle parts of general logic circuits even when they are performing useful computation. Experimental results on a set of MCNC benchmark circuits in a predictive 70nm process exhibits improvements of 15% to 88% in total active power compared to the results obtained by a conventional optimization flow.