Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel synthesis approach for active leakage power reduction using dynamic supply gating
Proceedings of the 42nd annual Design Automation Conference
Probabilistic dual-Vth leakage optimization under variability
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Digital Circuit Optimization via Geometric Programming
Operations Research
Dynamic power management under uncertain information
Proceedings of the conference on Design, automation and test in Europe
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
Proceedings of the 45th annual Design Automation Conference
Resilient dynamic power management under uncertainty
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Uncertainty-aware dynamic power management in partially observable domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Biologically-Inspired optimization of circuit performance and leakage: a comparative study
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Low-power circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal selection of Vth under a statistical model of threshold variation. Probabilistic analytical models are introduced to account for the impact of Vth uncertainty on leakage power and timing slack. Using this model, we show that the non-probabilistic analysis significantly (by 3x) underestimates the leakage power. We also show that in the presence of variability the optimal value of the second Vth must be about 30mV higher compared to the variation-free scenario. In addition, this model provides a way to compute the optimal value of the second Vth for a variety of process conditions.