Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Transistor-specific delay modeling for SSTA
Proceedings of the conference on Design, automation and test in Europe
Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
False Path Aware Timing Yield Estimation under Variability
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MODEST: a model for energy estimation under spatio-temporal variability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 48th Design Automation Conference
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With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic conditions during operation. In this paper, we present a multivariate regression based technique that computes the propagation delay of circuits subject to manufacturing process variations in the presence of temporal variations like temperature. It can be used to predict the dynamic behavior of circuits under changing operating conditions. The median error between the proposed model and circuit-level simulations is below 5%. With this model, we ran a study of the effect of temperature on access time delays for 500 cache samples. The study was run in 0.557 seconds, compared to the 20h and 4min of the SPICE simulation achieving a speedup of over 1 X 105. As a case study, we show that the access times of caches can vary as much as 2.03X at high temperatures in future technologies under process variations.