Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS

Authors:
Qikai Chen;Hamid Mahmoodi;Swarup Bhunia;Kaushik Roy
Affiliations:
Purdue University;Purdue University;Purdue University;Purdue University
Venue:
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Year:
2005

Citing 0
Cited 14

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Abstract

In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a novel low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.