Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations

Authors:
Shahinsdc Golshan;Amin Khajeh;Houman Homayoun;Eli Bozorgzadeh;Ahmed Eltawil;Fadi J. Kurdahi
Affiliations:
University of California at Irvine, Irvine, CA, USA;University of California at Irvine, Irvine, CA, USA;University of California at Irvine, Irvine, CA, USA;University of California at Irvine, irvine, CA, USA;University of California at Irvine, Irvine, CA, USA;University of California at Irvine, Irvine, CA, USA
Venue:
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2011

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Abstract

With advances in technology scaling, the configuration memory in SRAM-based FPGA is contributing a large portion of power consumption. Voltage scaling has been widely used to address the increases in power consumption in submicron regimes. However, with the advent of process variation in the configuration SRAMs, voltage scaling can undermine the integrity of a design implemented on the FPGA device as the design's functionality is determined by the contents of the configuration SRAMs. In this paper, we propose to exploit the abundance of homogenous resources on FPGA, in order to realize voltage scaling in the presence of process variation. Depending on the design to be implemented on FPGA, we select the minimal voltage that sustains a reliable placement. We then introduce a novel 2-phase placement algorithm that maximizes the reliability of the implemented design when voltage scaling is applied to the configuration memory. In the first phase, pre-deployment placement, we maximize the reliability of the implemented designs considering the a priori distribution of SRAM failures due to process variation and voltage scaling. The second phase, post-deployment placement, is performed once the device is fabricated in order to determine a fault-free placement of the design for the FPGA device. Our results indicate significant leakage power reduction (more than 50%) in the configuration memory when our placement technique is combined with voltage scaling with little delay degradation.