Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On power and fault-tolerance optimization in FPGA physical synthesis
Proceedings of the International Conference on Computer-Aided Design
Transformation from ad hoc EDA to algorithmic EDA
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
The survivability of design-specific spare placement in FPGA architectures with high defect rates
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance
Proceedings of the 50th Annual Design Automation Conference
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When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve injecting spare resources. However, these methods use predetermined spare placement that is not optimized for each netlist. This is the first work (to the best of our knowledge) that addresses the problem of fault tolerance for nano-FPGAs at the placement stage; fault tolerant placements are generated that are amenable to fast defect reconfiguration through replacement of defective logic elements with spares. We propose a simulated-annealing based placement algorithm that produces placements with the objective of maximizing the chances of successful recovery from faults in logic elements within the circuit's timing constraints. In addition, our study of the fault reconfiguration problem shows it is NP-Complete, and we propose a fast scheme for achieving a good reconfiguration solution for a random or clustered fault map. Experimental results show that these techniques can increase the probability of successful fault reconfiguration by 55% (compared to a uniform spare distribution scheme), without significantly degrading the circuit performance.