Compression-relaxation: a new approach to performance driven placement for regular architectures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Fault tolerant placement and defect reconfiguration for nano-FPGAs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Transformation from ad hoc EDA to algorithmic EDA
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
The survivability of design-specific spare placement in FPGA architectures with high defect rates
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A Field Programmable Gate Array (FPGA) consists of an array of identical configurable logic blocks (CLBs), each capable of implementing any boolean function with a bounded number of inputs. Such architectural regularity provides an inherent redundancy which can be exploited for fault tolerance and yield enhancement. In this paper we examine the problem of reconfiguring the placement of a circuit on an FPGA to tolerate a given fault pattern in the array of CLBs. The primary objective of the placement reconfiguration is to minimize timing degradation. The secondary objective is to minimize the amount of re-programming (both in the CLBs and in the routing switches) in the reconfiguration process. The concept of a slack neighborhood graph is introduced as a general tool for timing driven reconfiguration with a bounded increase in critical path delay. Our algorithm simultaneously achieves both provably low timing degradation and low reprogramming cost. Slack neighborhood graphs are of independent interest due to their possible applications to the timing driven placement problem. For a wide range of fault probabilities and circuits our algorithm successfully reconfigures the placement with less than 1% degradation in the circuit delay.