Efficiently supporting fault-tolerance in FPGAs

  • Authors:
  • John Lach;William H. Mangione-Smith;Miodrag Potkonjak

  • Affiliations:
  • UCLA EE Department, 56-125B Engineering IV, Los Angeles, CA;UCLA EE Department, 56-125B Engineering IV, Los Angeles, CA;UCLA CS Department, 4532K Boelter Hall, Los Angeles, CA

  • Venue:
  • FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
  • Year:
  • 1998

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Abstract

While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of realiability with low timing and hardware overhead.