Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Low overhead fault-tolerant FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
The method of parallel-sequential built-in self-testing in integrated circuits of the type SFPGAS
Automation and Remote Control
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A procedure to design reconfigurable systems capable to recover their operability in the case of fault of an arbitrary EPLD cell or connection was proposed. The most important advantages of the procedure lie in the retention of the signal propagation delays guaranteeing system operability after reconfiguration, as well as in low redundancy of the fault-tolerant system which at the limit may correspond only to one standby cell. The package methods enable one to design fault-tolerant systems based on the closed intelligent core without their upgrading. Efficiency of the procedure was estimated, and possible limitations of its application were discussed.