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FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
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Molecular electronics: devices, systems and tools for gigagate, gigabit chips
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Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Defect-tolerant Logic with Nanoscale Crossbar Circuits
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MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
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SCT: A novel approach for testing and configuring nanoscale devices
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ACM Journal on Emerging Technologies in Computing Systems (JETC)
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
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Vision for cross-layer optimization to address the dual challenges of energy and reliability
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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To tolerate defects in molecular electronics, the authors propose techniques to bypass defective resources during the logic mapping phase. These techniques take advantage of intrinsic redundancy in molecular crossbars to tolerate defective nanowires and nanocrossbars. The proposed greedy mapping algorithm can tolerate a defect density of 10% with very low area overheads.