RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Programmable logic circuits based on ambipolar CNFET
Proceedings of the 45th annual Design Automation Conference
Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
Proceedings of the 46th Annual Design Automation Conference
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nanowire crossbar logic and standard cell-based integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Imperfection-immune VLSI logic circuits using carbon nanotube field effect transistors
Proceedings of the Conference on Design, Automation and Test in Europe
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
A physical design tool for carbon nanotube field-effect transistor circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Layout-driven robustness analysis for misaligned carbon nanotubes in CNTFET-based standard cells
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS due to excellent CV/I device performance. An ideal CNFET inverter fabricated using a perfect CNFET technology can have 5.1 times faster F04 delay and 2.6 times lower energy per cycle compared to a 32nm Silicon CMOS inverter. Two fundamental challenges prevent us from creating CNFET-based logic designs with the advantages quoted above: 1. Misaligned Carbon Nanotubes (CNTs), and 2. Metallic CNTs. Misaligned CNTs can result in incorrect logic function implementations. This paper presents a technique for designing CNFET-based arbitrary logic functions that are guaranteed to be correct even in the presence of a large number of misaligned CNTs.