Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Automated design of misaligned-carbon-nanotube-immune circuits
Proceedings of the 44th annual Design Automation Conference
Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits
Proceedings of the conference on Design, automation and test in Europe
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Carbon nanotube circuits in the presence of carbon nanotube density variations
Proceedings of the 46th Annual Design Automation Conference
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
Proceedings of the 46th Annual Design Automation Conference
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement
Proceedings of the 47th Design Automation Conference
Imperfection-immune VLSI logic circuits using carbon nanotube field effect transistors
Proceedings of the Conference on Design, Automation and Test in Europe
Design and analysis of a new carbon nanotube full adder cell
Journal of Nanomaterials
A physical design tool for carbon nanotube field-effect transistor circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Layout-driven robustness analysis for misaligned carbon nanotubes in CNTFET-based standard cells
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today's grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET Design Kit (DK) to realize a complete design flow from logic-to-GDSII traversing the conventional CMOS design flow. This flow enables a framework that allows accurate comparison between CMOS and CNFET-based circuits. This paper also presents simulation results to illustrate such analysis, namely, a CNFET-based inverter can achieve gains, with respect to the Energy-Delay Product (EDP) metric, of more than 4x in delay, 2x in energy/cycle and significant area savings (more than 30%) when compared to a corresponding CMOS inverter benchmarked with an industrial 65nm technology.