Design and analysis of a new carbon nanotube full adder cell

Authors:
M. H. Ghadiry;Asrulnizam Abd Manaf;M. T. Ahmadi;Hatef Sadeghi;M. Nadi Senejani
Affiliations:
School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia;School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia;Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Skudai, Malaysia;Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Skudai, Malaysia;Department of Computer Engineering, Islamic Azad University, Ashtian, Iran
Venue:
Journal of Nanomaterials
Year:
2011

Citing 7
Cited 0

Current-voltage characteristics of a silicon nanowire transistor

Microelectronics Journal
Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Dynamic Power High Performance Adder

ICFCC '09 Proceedings of the 2009 International Conference on Future Computer and Communication
A novel low-power full-adder cell for low voltage

Integration, the VLSI Journal
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis

Proceedings of the Conference on Design, Automation and Test in Europe
Graphene nanoribbon conductance model in parabolic band structure

Journal of Nanomaterials - Special issue on Graphene
High-performance carbon nanotube field-effect transistor with tunable polarities

IEEE Transactions on Nanotechnology

Quantified Score

Hi-index	0.00

Visualization

Abstract

A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.