Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Low Power Energy Recovery Full Adder Cell
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
A Novel Technique for Noise-Tolerance in Dynamic Circuits
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
A fast and power-area-efficient accumulator for flying-adder frequency synthesizer
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Circuits and Systems II: Express Briefs
A low power gate level full adder module
ASMCSS'09 Proceedings of the 3rd International Conference on Applied Mathematics, Simulation, Modelling, Circuits, Systems and Signals
ULPFA: a new efficient design of a power-aware full adder
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proposed low power, high speed adder-based 65-nm Square root circuit
Microelectronics Journal
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
WSEAS Transactions on Circuits and Systems
CMOS full-adders for energy-efficient arithmetic applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of a new carbon nanotube full adder cell
Journal of Nanomaterials
Design of 9-transistor single bit full adder
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Investigating the impact of logic and circuit implementation on full adder performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
Integration, the VLSI Journal
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We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous XOR-XNOR signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4-and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders.