IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
Designing high-speed adders in power-constrained environments
IEEE Transactions on Circuits and Systems II: Express Briefs
A low power gate level full adder module
ASMCSS'09 Proceedings of the 3rd International Conference on Applied Mathematics, Simulation, Modelling, Circuits, Systems and Signals
High speed, low power 8t full adder cell with 45% improvement in threshold loss problem
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
A survey of low power high speed one bit full adder
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
A novel CMOS 1-bit 8T full adder cell
WSEAS TRANSACTIONS on SYSTEMS
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
WSEAS Transactions on Circuits and Systems
A new optimized high-speed low-power data-driven dynamic (d3l) 32-bit kogge-stone adder
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Performance analysis of radix-4 adders
Integration, the VLSI Journal
Logic style comparison for ultra low power operation in 65nm technology
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Design of 9-transistor single bit full adder
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
Integration, the VLSI Journal
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A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low powerful1 adders; the transmission function adder (TFA), the dual value logic (DVL) adder and the fourteen transistor (14T)full adder. The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder. The combination of low power and low transistor count makes the new SERF cell a viable option for low power design.