A novel low-power full-adder cell for low voltage

Authors:
Keivan Navi;Mehrdad Maeen;Vahid Foroutan;Somayeh Timarchi;Omid Kavehei
Affiliations:
Faculty of Electrical and Computer Engineering, Shahid Beheshti University GC, Tehran, Iran;Microelectronic LAB of Shahid Beheshti University and IAU, Tehran, Iran;Microelectronic LAB of Shahid Beheshti University and IAU, Tehran, Iran;Faculty of Electrical and Computer Engineering, Shahid Beheshti University GC, Tehran, Iran;School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, SA 5005, Australia
Venue:
Integration, the VLSI Journal
Year:
2009

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Abstract

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-@mm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.