Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Low Power Energy Recovery Full Adder Cell
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Microelectronic Engineering
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
High-speed full adder based on minority function and bridge style for nanoscale
Integration, the VLSI Journal
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages
International Journal of High Performance Systems Architecture
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A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18@mm and 90nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.