Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A high density, carbon nanotube capacitor for decoupling applications
Proceedings of the 43rd annual Design Automation Conference
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
On single-electron technology full adders
IEEE Transactions on Nanotechnology
Modeling SWCNT Bandgap and Effective Mass Variation Using a Monte Carlo Approach
IEEE Transactions on Nanotechnology
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In this paper a novel carbon nanotube field effect transistor-based CNFET one bit full adder cell is presented for low voltage applications. Since in CNFET technology the threshold voltage Vth of each transistor can be easily changed by the alteration of the diameters of its carbon nanotubes CNTs, a multi-threshold full adder cell is designed in this paper. In order to have accurate comparisons with some classical and state-of-the-art metal-oxide-semiconducting field-effect transistor MOSFET and CNFET based designs, comprehensive simulations with respect to various load capacitances, frequencies, and temperatures have been performed. Simulation results confirm the superiority of the proposed design in terms of delay, power consumption, and power-delay product PDP, against the other ones. Moreover, since the process fluctuations of today's sub-micron technologies are the most important concern, a Monte Carlo transient analysis in the presence of the mismatches of the CNT diameters is performed. This simulation shows that the proposed cell is reliable and functions properly in the presence of the diameter fluctuations of the CNTs.