On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient decoupling capacitor planning via convex programming methods
Proceedings of the 2006 international symposium on Physical design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes
IEEE Transactions on Nanotechnology
Electrical models for vertical carbon nanotube capacitors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
High-speed full adder based on minority function and bridge style for nanoscale
Integration, the VLSI Journal
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages
International Journal of High Performance Systems Architecture
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We present a novel application for carbon nanotube devices, implementing a high density 3-D capacitor, which can be useful for decoupling applications to reduce supply voltage variations. The capacitor consists of staggered layers of interleaved carbon nanotubes, alternately connected to anode and cathode contacts. The device can realize a capacitance/area, significantly larger than the ITRS's projected requirements for year 2018. The capacitance per unit area can exceed 1pF/μm2, with a quality factor greater than 100 at 1GHz.