Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high density, carbon nanotube capacitor for decoupling applications
Proceedings of the 43rd annual Design Automation Conference
Six subthreshold full adder cells characterized in 90 nm CMOS technology
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability
Integration, the VLSI Journal
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the Reliability of Majority Gates Full Adders
IEEE Transactions on Nanotechnology
International Journal of High Performance Systems Architecture
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In this paper a new high-speed and high-performance Full Adder cell, which is implemented based on CMOS bridge style and minority function, is proposed. Several simulations conducted at nanoscale using different power supplies, load capacitors, frequencies and temperatures demonstrate the superiority of the proposed design in terms of delay and power-delay product (PDP) compared to the other cells. In addition the proposed structure improves the robustness and reduces sensitivity to the process variations of the other Bridge-Cap Full Adder cell already presented in the literature.