Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Low-power design techniques for high-performance CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS Logic Circuit Design
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the Reliability of Majority Gates Full Adders
IEEE Transactions on Nanotechnology
A new quantum-dot cellular automata full-adder
Microelectronics Journal
High-speed full adder based on minority function and bridge style for nanoscale
Integration, the VLSI Journal
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
Integration, the VLSI Journal
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Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18@mm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).