Design techniques for high performance, energy efficient control logic
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
High performance DSPs - what's hot and what's not?
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Scalable Hardware-Algorithms for Binary Prefix Sums
IEEE Transactions on Parallel and Distributed Systems
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A novel charge recycling design scheme based on adiabatic charge pump
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New low-power tristate circuits in positive feedback source-coupled logic
Journal of Electrical and Computer Engineering
Hi-index | 0.00 |
A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 /spl mu/m CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V.