Low-power design techniques for high-performance CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering
Journal of VLSI Signal Processing Systems
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
A new EDA defined interchange format for processing of dependence graphs
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
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In this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance and power dissipation. This architecture is then extended to derive a configurable processor array (CPA), which is configurable for filter order, sample period and power reduction factor. The hardware overhead incurred for configurability is minimal.