A modular systolic architecture for delayed least mean squares adaptive filtering
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering
Journal of VLSI Signal Processing Systems
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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Existing systolic architectures for the LMS algorithm with delayed coefficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolic architecture with minimal adaptation delay and input/output latency, thereby improving the convergence behaviour to near that of the original LMS algorithm. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the delayed LMS algorithm. With the use of carry-save arithmetic, the systolic folded pipelined architecture can support very high sampling rates, limited only by the delay of a full adder.