Adaptive signal processing
VLSI array processors
Adaptive filter theory (2nd ed.)
Adaptive filter theory (2nd ed.)
Multirate systems and filter banks
Multirate systems and filter banks
High-level algorithm and architecture transformations for DSP synthesis
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of pipelined DSP accelerators with dynamic scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of an ASIP architecture for low-level visual elaborations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable VLSI coprocessing system for the block matching algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay
Integration, the VLSI Journal
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Over-Sampling Subband Adaptive Filter with the Optimal Real Filter Bank
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97)-Volume 3 - Volume 3
Reconfigurable Processing: The Solution to Low-Power Programmable DSP
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
A subband adaptive filter with the optimum analysis filter bank
ICASSP '95 Proceedings of the Acoustics, Speech, and Signal Processing, 1995. on International Conference - Volume 02
Low-power adaptive filter architectures and their application to51.84 Mb/s ATM-LAN
IEEE Transactions on Signal Processing
H∞ optimality of the LMS algorithm
IEEE Transactions on Signal Processing
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
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Architectural synthesis of low-power computational engines (hardware accelerators) for a subband-based adaptive filtering algorithm is presented. The full-band least mean square (LMS)adaptive filtering algorithm, widely used in various applications, is confronted by two problems, viz., slow convergence when the inputcorrelation matrix is ill-conditioned, and increased computational complexity for applications involving use of large adaptive filter orders. Both of these problems can be overcome by the use of a subband-based normalized LMS (NLMS) adaptive filtering algorithm. Since this algorithm is not amenable to pipelining, delayed coefficient adaptation in the NLMS updation is used, which provides the required delays for pipelining. However, the convergence speed of this subband-based delayed NLMS (DNLMS) algorithm degrades with increase inthe adaptation delay. We first present a pipelined subband DNLMS adaptive filtering architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preservingtransformations on the signal flow graph (SFG) representation of thesubband DNLMS algorithm. With the use of carry-save arithmetic,the pipelined architecture can support high sampling rateslimited only by the delay of two full adders and a 2-to-1multiplexer. We then extend this synthesis methodology to synthesize a pipelined subband DNLMS architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the subband DNLMS algorithm to meet the required computationalthroughput. The architecture exhibits a novel tradeoff betweenalgorithmic performance (convergence speed) and powerdissipation. Finally, we incorporate configurability for filter order,sample period, power reduction factor, number of subbands anddecimation/interpolation factor in the low-power architecture,thus resulting in a low-power subband computational engine for adaptivefiltering.